1. Field of the Invention
The present invention relates to fabrication of semiconductor integrated circuits and, more particularly, to improved methods for chemically assisted etch processing in a plasma processing system.
2. Description of the Related Art
In the fabrication of semiconductor-based devices, e.g., integrated circuits or flat panel displays, layers of materials may alternately be deposited onto and etched from a substrate surface. During the fabrication process, various layers of material, e.g., borophosphosilicate glass (BPSG), polysilicon, metal, and etc., are deposited on the substrate and patterned with a photoresist process. Thereafter, portions of the layers can be etched away to form various features, e.g., interconnect lines, via connections, trenches, and etc.
The process of etching may be accomplished by a variety of known techniques, including plasma-enhanced etching. In plasma-enhanced etching, the actual etching typically takes place inside a plasma processing chamber of a plasma processing system. To form the desired pattern on the substrate surface, an appropriate mask (e.g., a photoresist mask) is typically provided. With the substrate in the plasma processing chamber, a plasma is then formed from a suitable etchant source gas, or mixture of gases. The plasma is used to etch areas that are left unprotected by the mask, thereby forming the desired pattern. In this manner, portions of the layers are etched away to form interconnect lines, via connections, trenches, and other features. The deposition and etching processes may be repeated until the desired circuit is obtained.
Fabrication of the modern integrated circuits continues to challenge those skilled in the art to find new techniques to enhance the control over the etching process. By way of example, as the features for the modern integrated circuits have been reduced in size, it has become increasingly more difficult to etch the desired features using conventional etching techniques. To elaborate, as features have become increasingly smaller, it has become increasingly more difficult to achieve a uniform etch rate for the etching processes. For example, it has become increasingly more difficult to achieve the same etch rate for the regions where the features are relatively closely spaced and for the regions where the features are in relatively wider spacing. This problem has been referred to as the micro loading effect.
In order to overcome a variety of the problems associated with etching of increasing smaller features in the modern integrated circuit, more recent techniques have proposed alternative chemistries for the etchant source gases. By way of example, one recent development has identified innovative chemistries that can enhance selectivity, in addition to effectively reducing the effects of micro loading. For example, one such innovative chemistries is the combination of C4F, N2, and Ar which is described in the U.S. Pat. No. 6,090,304, filed on Aug. 28, 1997.
Although chemistries such as the combination of C4F, N2, and Ar are effective against micro loading and can significantly enhance selectivity, unfortunately, these chemistries are not suitable for situations where critical dimensions of the etched features are an important consideration, e.g., situations where relatively small features are to be etched and the margin for error is relatively smaller. To elaborate, in some etching processes, there is a difference between the desired (or pre-etch) critical dimension and the post-etch critical dimension of a feature. This difference can be referred to as the critical dimension bias. The critical dimension bias, as used herein, refers to the difference between a desired (or the pre-etch) dimension and the corresponding post etch dimension of a feature. Usually, the etching process results in enlarging the critical dimension of a feature.
To facilitate discussion of the critical dimension bias, FIGS. 1 and 2, respectively, illustrate a cross section view of a pre-etch wafer 100 and a cross section view of a post-etch wafer 200. Wafer 100 is shown as having a layer stack 102 disposed above the surface of a substrate 104, e.g., silicon. The layer stack 102 includes an oxide layer 106, a polysilicon layer 108, and a dielectric layer 110. The oxide layer 106, typically comprising SiO2, is disposed above silicon substrate 104. Above oxide layer 106, there may be disposed a polysilicon layer 108. A dielectric layer 110, e.g., a BPSG, a PSG, a SiO2, or a TEOS layer 110, may be disposed above the polysilicon layer 108.
A distance D1 (between masked regions 112a and 112b) represents the desired (or pre-etch) width dimension of a feature that is to be etched through the layer 110 via an open area 118. By way of example, for relatively small features, distance D1 can be about 0.25 xcexcm.
After the etching process as illustrated in FIG. 2, a region 120 is formed. The region 120 extends through the layer 110 and a portion of the layer 108. A distance (gap) D2 represents the post-etch width dimension of the feature that has been etched in the region 120. The distance D2 is significantly larger than distance D1. By way of example, it is not uncommon for the distance D2 to be 0.05 xcexcm larger than distance D1. However, for small features, such as 0.25 xcexcm, a variation of 0.05 xcexcm represents an increase of about 20%.
As appreciated by those skilled in the art, such a significant difference between distances D1 and D2 (critical dimension bias) is highly undesirable. The critical dimension bias can cause a multitude of problems in the fabricated Integrated circuit. By way of example, an enlarged etched feature can overlap with another etched feature. Overlapping etched features can render the integrated circuit defective.
Moreover, as the size of the modern integrated circuit has been reduced, the distances between etched features, e.g., interconnect lines, via connections, trenches, and other features, have become increasingly smaller. In other words, in the modern integrated circuits, the margin of error (i.e., deviation from the required dimensions as required by the specification) for the etched features, has become increasing smaller and smaller. Thus, the margin of error is also becoming smaller and smaller. As such, the critical dimension bias has become a substantial problem.
In view of foregoing, there is a need for improved etching techniques that effectively reduce critical dimension bias.
Broadly speaking, the invention relates to improved methods for chemically assisted etch processing in a plasma processing system. Some embodiments of the invention are summarized below.
In one embodiment a plasma processing system, including a plasma processing chamber suitable for use with the improved methods of the present application, is described. The disclosed plasma processing system can be utilized to perform an etch process for a selected layer of material that is deposited on a wafer substrate. The selected layer of material can be deposited using a known deposition method.
In another embodiment a method for etching through a selected portion of a deposited dielectric layer is described. The dielectric layer can be deposited on a wafer substrate by a conventional deposition method. The method for etching through the selected portion of the deposited dielectric layer is performed in a plasma processing chamber. A wafer substrate having a deposited layer identified for etching is placed in the plasma processing system. An etchant source gas that consists primarily of a combination of C3F6 and O2 gases is introduced into the plasma processing chamber. The etchant source gas, the temperature and the pressure in the processing chamber are stabilized. Then the electrodes in the plasma processing chamber are powered up to ignite the plasma to perform the etching process, in accordance with this embodiment of the present invention.
This invention has numerous advantages. One advantage is that the critical dimension bias that is associated with the etch process is effectively reduced. Another advantage is that other undesirable side effects of the etching process, e.g., bowing, micro loading, passivation, etc., can be curtailed. Yet another advantage is that features with higher aspect ratios can be etched in accordance with the improved techniques of the present invention.
Other aspects and advantages of the invention will become apparent from the following detailed description, taken in conjunction with the accompanying drawings illustrating, by way of example, the principles of the invention.